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? semiconductor components industries, llc, 2013 may, 2013 ? rev. 7 1 publication order number: ncp1080/d ncp1080 integrated poe-pd & dc-dc converter controller introduction the ncp1080 is a member of on semiconductor?s power over ethernet powered device (poe ? pd) product family and represents a robust, flexible and highly integrated solution targeting demanding ethernet applications. it combines in a single unit an enhanced poe ? pd interface fully supporting the ieee802.3af specification and a flexible and configurable dc ? dc converter controller. the ncp1080?s exceptional capabilities offer new opportunities for the design of products powered directly over ethernet lines, eliminating the need for local power adaptors or power supplies and drastically reducing the overall installation and maintenance cost. on semiconductor?s unique manufacturing process and design enhancements allow the ncp1080 to deliver up to 13 w of regulated power to support poe applications according to the ieee802.3af standard. this device leverages the significant cost advantages of poe ? enabled systems to a broad spectrum of products in markets such as voip phones, wireless lan access point, security cameras, point of sales terminals, rfid readers, industrial ethernet devices, etc. the integrated current mode dc ? dc controller facilitates isolated and non ? isolated fly ? back, forward and buck converter topologies. it has all the features necessary for a flexible, robust and highly ef ficient design including programmable switching frequency, duty cycle up to 80 percent, slope compensation, and soft start ? up. the ncp1080 is fabricated in a robust high voltage process and integrates a rugged vertical n ? channel dmos with a low loss current sense technique suitable for the most demanding environments and capable of withstanding harsh environments such as hot swap and cable esd events. the ncp1080 complements on semiconductor?s assp portfolio in communications and industrial devices and can be combined with other high ? voltage interfacing devices to offer complete solutions to the communication, industrial and security markets. features ? these are pb ? free devices powered device interface ? fully supports ieee802.3af standard ? regulated power output up to 13 w ? programmable classification current ? adjustable under voltage lock out ? programmable inrush current limit ? programmable operational current limit up to 500 ma ? over ? temperature protection ? industrial t emperature range ? 40 c to 85 c with full operation up to 150 c junction temperature ? 0.6 hot ? swap pass ? switch with low loss current sense technique ? vertical n ? channel dmos pass ? switch offers the robustness of discrete mosfets with integrated temperature control dc ? dc converter controller ? current mode control ? supports isolated and non ? isolated dc ? dc converter applications ? internal voltage regulators ? wide duty cycle range with internal slope compensation circuitry ? programmable oscillator frequency ? programmable soft ? start time http://onsemi.com ncp1080 = specific device code xxxx = date code y = assembly location zz = traceability code tssop ? 20 ep de suffix case 948ab see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information 1
ncp1080 http://onsemi.com 2 (top view) pin diagram exposed pad 1 ss fb comp vddl vddh gate artn nc cs osc vportp class uvlo inrush ilim1 vportn1 rtn vportn2 test1 test2 ordering information part number package shipping configuration ? temperature range ncp1080deg tssop ? 20 ep (pb ? free) 74 units / tube ? 40 c to 85 c NCP1080DER2G tssop ? 20 ep (pb ? free) 2500 / tape & reel ? 40 c to 85 c ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. figure 1. ncp1080 block diagram internal supply vddh inrush ilim1 classification detection vportn1,2 vportp class inrush ilim1 vddh nc vddl thermal hot swap switch control & current limit blocks uvlo uvlo rtn artn 1.2 v dc ? dc control osc ss fb comp cs gate vddl vddl vddl vddh 5 k osc vddl converter 5 a shut down monitor vport & bandgap
ncp1080 http://onsemi.com 3 simplified application diagrams figure 2. isolated fly ? back converter ld1 rd1 ncp1080 cline spare pairs rcs cvddh cpd css rosc m1 t1 cload rclass rilim1 rinrush r1 r2 optocoupler r3 r4 r5 c1 z1 rslope c2 voutput rj ? 45 d1 db1 db2 oc1 z_line gate rtn fb comp vportn2 vddh vddl osc ss vportn1 class artn ilim1 inrush test1 test2 uvlo cs vportp cvddl data pairs figure 2 shows the integrated poe ? pd switch and dc ? dc controller configured to work in a fully isolated application. the output voltage regulation is accomplished with an external opto ? coupler and a shunt regulator (z1). figure 3. non ? isolated fly ? back converter ncp1080 gate rtn fb comp vportn2 vddh vddl rcs cvddh cpd c1comp c2comp rcomp osc ss m1 t1 r4 vportn1 class artn ilim1 inrush test1 test2 rclass rilim1 rinrush uvlo cs vportp rslope voutput cline spare pairs r1 r2 rj ? 45 db1 db2 z_line ld1 rd1 cvddl data pairs css rosc r3 cload figure 3 shows the integrated poe ? pd and dc ? dc controller configured in a non ? isolated fly ? back configuration. a compensation network is inserted between the fb and the comp pin for overall stability of the feedback loop.
ncp1080 http://onsemi.com 4 simplified application diagrams figure 4. non ? isolated fly ? back with extra winding cpd ncp1080 gate rtn fb comp vportn2 vddh vddl rcs cvddh c1comp c2comp rcomp osc ss css m1 r4 vportn1 class artn ilim1 inrush test1 test2 rclass rilim1 rinrush r1 r2 uvlo cs vportp rslope d1 d2 t1 r5 voutput cline spare pairs rj ? 45 db1 db2 z_line ld1 rd1 cvddl r3 cload rosc data pairs figure 4 shows the same non ? isolated fly ? back configuration as figure 3, but adds a 12 v auxiliary bias winding on the transformer to provide power to the ncp1080 dc ? dc controller via its vddh pin. this topology shuts off the current flowing from vportp to vddh and therefore reduces the internal power dissipation of the pd, resulting in higher overall power efficiency. figure 5. non ? isolated forward converter cpd ncp1080 gate rtn fb comp vportn2 vddh vddl rcs cvddh c1comp c2comp rcomp osc ss css m1 cload r3 r4 vportn1 class artn ilim1 inrush test1 test2 rclass rilim1 rinrush r1 r2 uvlo cs vportp l1 rslope voutput t1 d1 d2 d3 cline spare pairs rj ? 45 db1 db2 z_line ld1 rd1 cvddl data pairs rosc figure 5 shows the ncp1080 used in a non ? isolated forward topology.
ncp1080 http://onsemi.com 5 table 1. pin descriptions name pin no. type description vportp 1 supply positive input power. voltage with respect to vportn 1,2 vportn1 vportn2 6,8 ground negative input power. connected to the source of the internal pass ? switch. rtn 7 ground dc ? dc controller power return. connected to the drain of the internal pass ? switch. it must be connected to artn. this pin is also the drain of the internal pass ? switch. artn 14 ground dc ? dc controller ground pin. must be connected to rtn as a single point ground connection for improved noise immunity. vddh 16 supply output of the 9 v ldo internal regulator. voltage with respect to artn. supplies the internal gate driver. vddh must be bypassed to artn with a 1 f or 2.2 f ceramic capacitor with low esr. vddl 17 supply output of the 3.3 v ldo internal regulator. voltage with respect to artn. this pin can be used to bias an external low ? power led (1 ma max.) connected to artn, and can also be used to add extra biasing current in the external opto ? coupler. vddl must be bypassed to artn with a 330 nf or 470 nf ceramic capacitor with low esr. class 2 input classification current programming pin. connect a resistor between class and vportn 1,2 . inrush 4 input inrush current limit programming pin. connect a resistor between inrush and vportn 1,2 . ilim1 5 input operational current limit programming pin. connect a resistor between ilim1 and vportn 1,2 . uvlo 3 input dc ? dc controller under ? voltage lockout input. voltage with respect to vportn 1,2 . connect a resistor ? divider from vportp to uvlo to vportn 1,2 to set an external uvlo threshold. gate 15 output dc ? dc controller gate driver output pin. osc 11 input internal oscillator frequency programming pin. connect a resistor between osc and artn. nc 13 no connect pin, must not be connected. comp 18 i/o output of the internal error amplifier of the dc ? dc controller. comp is pulled ? up internally to vddl with a 5 k resistor. in isolated applications, comp is connected to the collector of the opto ? coupler. voltage with respect to artn. fb 19 input dc ? dc controller inverting input of the internal error amplifier. in isolated applications, the pin should be strapped to artn to disable the internal error amplifier. cs 12 input current ? sense input for the dc ? dc controller. voltage with respect to artn. ss 20 input soft ? start input for the dc ? dc controller. a capacitor between ss and artn determines the soft ? start timing. test1 9 input digital test pin must always be connected to vportn 1,2 . test2 10 input digital test pin must always be connected to vportn 1,2 . ep exposed pad. connected to vportn 1,2 ground.
ncp1080 http://onsemi.com 6 table 2. absolute maximum ratings symbol parameter min. max. units conditions vportp input power supply ? 0.3 72 v voltage with respect to vportn 1,2 rtn artn analog ground supply 2 ? 0.3 72 v pass ? switch in off ? state (voltage with respect to vportn 1,2 ) vddh internal regulator output ? 0.3 17 v voltage with respect to artn vddl internal regulator output ? 0.3 3.6 v voltage with respect to artn class analog output ? 0.3 3.6 v voltage with respect to vportn 1,2 inrush analog output ? 0.3 3.6 v voltage with respect to vportn 1,2 ilim1 analog output ? 0.3 3.6 v voltage with respect to vportn 1,2 uvlo analog input ? 0.3 3.6 v voltage with respect to vportn 1,2 osc analog output ? 0.3 3.6 v voltage with respect to artn comp analog input / output ? 0.3 3.6 v voltage with respect to artn fb analog input ? 0.3 3.6 v voltage with respect to artn cs analog input ? 0.3 3.6 v voltage with respect to artn ss analog input ? 0.3 3.6 v voltage with respect to artn nc open pin test1 test2 digital inputs ? 0.3 3.6 v voltage with respect to vportn 1,2 t a ambient temperature ? 40 85 c t j junction temperature ? 150 c t j ? tsd junction temperature (note 1) ? 175 c thermal shutdown condition t stg storage temperature ? 55 150 c t ja thermal resistance, junction to air (note 2) 37.6 c/w exposed pad connected to vportn 1,2 ground esd ? hbm human body model 4 ? kv per jedec standard jesd22 esd ? cdm charged device model 750 ? v esd ? mm machine model 300 ? v lu latch ? up 200 ? ma per jedec standard jesd78 esd ? sys system esd (contact/air) (note 3) 8/15 ? kv stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. t j ? tsd allowed during error conditions only. it is assumed that this maximum temperature condition does not occur more than 1 hour cumulative during the useful life for reliability reasons. 2. mounted on a 1s2p (3 layer) test board with copper coverage of 25 percent for the signal layers and 90 percent copper coverag e for the inner planes at an ambient temperature of 85 c in still air. refer to jedec jesd51 ? 7 for details. 3. surges per en61000 ? 4 ? 2, 1999 applied between rj ? 45 and output ground and between adapter input and output ground of the evaluation board. the specified values are the test levels and not the failure levels.
ncp1080 http://onsemi.com 7 recommended operating conditions operating conditions define the limits for functional operation and parametric characteristics of the device. note that the functionality of the device outside the operating conditions described in this section is not warranted. operating outside the recommended operating conditions for extended periods of time may affect device reliability. all values concerning the dc ? dc controller, vddh and vddl blocks are with respect to artn. all others are with respect to vportn 1,2 (unless otherwise noted). table 3. operating conditions symbol parameter min. typ. max. units conditions input supply vport input supply voltage 0 57 v vport = vportp ? vportn 1,2 signature detection vsignature input supply voltage signature detection range 1.4 9.5 v rsignature signature resistance (note 4) 23.75 26.25 k offset_current i_vportp + i_rtn ? 1.8 5 a vportp = rtn = 1.4 v sleep_current i_vportp + i_rtn ? 15 25 a vportp = rtn = 9.5 v classification vcl input supply voltage classification range 13 20.5 v iclass0 class 0: rclass 10 k (note 5) 0 ? 4 ma iclass0 = i_vportp + i_rdet iclass1 class 1: rclass 130 (note 5) 9 ? 12 ma iclass1 = i_vportp + i_rdet iclass2 class 2: rclass 69.8 (note 5) 17 ? 20 ma iclass2 = i_vportp + i_rdet iclass3 class 3: rclass 44.2 (note 5) 26 ? 30 ma iclass3 = i_vportp + i_rdet iclass4 class 4: rclass 30.9 (note 5) 36 ? 44 ma iclass4 = i_vportp + i_rdet idc class internal current consumption during classification (note 6) ? 600 ? a for information only uvlo vuvlo_on default turn on voltage (vportp rising) 38 40 v uvlo pin tied to vportn 1,2 vuvlo_off default turn off voltage (vportp falling) 29.5 32 ? v uvlo pin tied to vportn 1,2 vhyst_int uvlo internal hysteresis ? 6 ? v uvlo pin tied to vportn 1,2 vuvlo_pr uvlo external programming range 25 ? 50 v uvlo pin connected to the resistor divider (r1 & r2). for information only vhyst_ext uvlo external hysteresis ? 15 ? % uvlo pin connected to the resistor divider (r1 & r2) uvlo_filter uvlo on/off filter time ? 90 ? s 4. test done according to the ieee802.3af 2 point measurement. the minimum probe voltages measured at the poe ? pd are 1.4 v and 2.4 v, and the maximum probe voltages are 8.5 v and 9.5 v. 5. measured with an external rdet of 25.5 k between vportp and vportn 1,2 , and for 13 v < vport < 20.5 v (with vport = vportp ? vportn 1,2 ). resistors are assumed to have 1% accuracy. 6. this typical current excludes the current in the rclass and rdet external resistors.
ncp1080 http://onsemi.com 8 table 3. operating conditions symbol parameter min. typ. max. units conditions pass ? switch and current limits ron pass ? switch rds ? on ? 0.6 1.2 max ron specified at tj = 130 c i_rinrush1 rinrush = 150 k (note 7) 95 125 155 ma measured at rtn ? vportn 1,2 = 3 v i_rinrush2 rinrush = 57.6 k (note 7) 260 310 360 ma measured at rtn ? vportn 1,2 = 3 v i_rilim1 rilim1 = 84.5 k (note 7) 450 510 570 ma current limit threshold inrush and ilim1 current limit transition vds_pgood vds required for power good status 0.8 1 1.2 v rtn ? vportn 1,2 falling; voltage with re- spect to vportn 1,2 vds_pgood_hyst vds hysteresis required for power good status ? 8.2 ? v voltage with respect to vportn 1,2 vddh regulator vddh_reg regulator output voltage (notes 8 and 9) ivddh_load + ivddl_load < 10 ma with 0 < ivddl_load < 2.25 ma 8.4 9 9.6 v vddh_off regulator turn ? off voltage ? vddh_reg + 0.5 v ? v for information only vddh_lim vddh regulator current limit (notes 8 and 9) 13 ? 26 ma vddh_por_r vddh por level (rising) 7.3 ? 8.3 v vddh_por_f vddh por level (falling) 6 ? 7 v vddh_ovlo vddh over ? voltage level (rising) 16 ? 18.5 v vddl regulator vddl_reg regulator output voltage (notes 8 and 9) 0 < ivddl_load < 2.25 ma with ivddh_load + ivddl_load < 10 ma 3.05 3.3 3.55 v vddl_por_r vddl por level (rising) vddl ? 0.2 ? vddl ? 0.02 v vddl_por_f vddl por level (falling) 2.5 ? 2.9 v gate driver gate_tr gate rise time (10 ? 90%) ? ? 50 ns cload = 2 nf, vddhreg = 9 v gate_tf gate fall time (90 ? 10%) ? ? 50 ns cload = 2 nf, vddhreg = 9 v pwm comparator vcomp comp control voltage range 1.3 ? 3 v for information only 7. the current value corresponds to the poe ? pd input current (the current flowing in the external rdet and the quiescent current of the device are included). resistors are assumed to have 1% accuracy. 8. power dissipation must be considered. load on vddh and vddl mu st be limited especially if vddh is not powered by an auxiliary winding. 9. ivddl_load = current flowing out of the vddl pin. ivddh_load = current flowing out of the vddh pin + current delivered to the gate driver (function of the frequency, vddh voltage & mosfet gate capacitance).
ncp1080 http://onsemi.com 9 table 3. operating conditions symbol parameter min. typ. max. units conditions error amplifier vbg_fb reference voltage 1.15 1.2 1.25 v voltage with respect to artn av_ol dc open loop gain ? 80 ? db for information only gbw error amplifier gbw 1 ? ? mhz for information only soft ? start vss soft ? start voltage range ? 1.15 ? v vss_r soft ? start low threshold (rising edge) 0.35 0.45 0.55 v iss soft ? start source current 3 5 7 a current limit comparator csth cs threshold voltage 324 360 396 mv tblank blanking time ? 100 ? ns for information only oscillator dutyc maximum duty cycle ? 80% ? fixed internally frange oscillator frequency range 100 ? 500 khz f_acc oscillator frequency accuracy 25 % current consumption ivportp 1 vportp internal current consumption (note 10) ? 2.5 3.5 ma dc ? dc controller off ivportp 2 vportp internal current consumption (note 11) ? 4.7 6.5 ma dc ? dc controller on thermal shutdown tsd thermal shutdown threshold 150 ? ? c tj t j = junction temperature thyst thermal hysteresis ? 15 ? c tj t j = junction temperature thermal ratings t a ambient temperature ? 40 ? 85 c t j junction temperature ? ? 125 150 c c parametric values guaranteed max 1000 hours 10. conditions a. no current through the pass ? switch b. dc ? dc controller inactive (ss shorted to rtn) c. no external load on vddh and vddl d. vportp = 57 v 11. conditions a. no current through the pass ? switch b. oscillator frequency = 100 khz c. no external load on vddh and vddl d. aux winding not used e. 2 nf on gate, dc ? dc controller enabled f. vportp = 57 v
ncp1080 http://onsemi.com 10 description of operation powered device interface the pd interface portion of the ncp1080 supports the ieee802.3af defined operating modes: detection signature, current source classification, inrush and operating current limits. in order to give more flexibility to the user and also to keep control of the power dissipation in the ncp1080, both current limits are configurable. the device enters operation once its programmable vuvlo_on threshold is reached, and operation ceases when the supplied voltage falls below the vuvlo_off threshold. sufficient hysteresis and uvlo filter time are provided to avoid false power on/off cycles due to transient voltage drops on the cable. detection during the detection phase, the incremental equivalent resistance seen by the pse through the cable must be in the ieee802.3af standard specification range (23.75 k to 26.25 k ) for a pse voltage from 2.7 v to 10.1 v. in order to compensate for the non ? linear effect of the diode bridge and satisfy the specification at low pse voltage, the ncp1080 presents a suitable impedance in parallel with the 25.5 k r det external resistor connected between vportp and vportn. for some types of diodes (especially schottky diodes), it may be necessary to adjust this external resistor. when the detection_off level is detected (typically 11.5 v) on vportp, the ncp1080 turns on its internal 3.3 v regulator and biasing circuitry in anticipation of the classification phase as the next step. classification once the pse device has detected the pd device, the classification process begins. in classification, the pd regulates a constant current source that is set by the external resistor rclass value on the class pin. figure 6 shows the schematic overview of the classification block. the current source is defined as: i class v bg r class , (where v bg is 1.2 v) class vdda1 1.2 v vportp vportn1,2 ncp1080 rclass figure 6. classification block diagram power mode when the classification hand ? shake is completed, the pse and pd devices move into the operating mode. under voltage lock out (uvlo) the ncp1080 incorporates an under voltage lock out (uvlo) circuit which monitors the input voltage and determines when to apply power to the dc ? dc controller. to use the default settings for uvlo (see t able 3), the pin uvlo must be connected to vportn 1,2 . in this case the signature resistor has to be placed directly between vportp and vportn 1,2 , as shown in figure 7. figure 7. default uvlo settings uvlo vportp vportn1,2 ncp1080 vport rdet to define the uvlo threshold externally, the uvlo pin must be connected to the center of an external resistor divider between vportp and vportn 1,2 as shown in figure 8. the series resistance value of the external resistors must add to 25.5 k and replaces the internal signature resistor. figure 8. external uvlo configuration uvlo vportn1,2 ncp1080 vport r2 r1 vportp for a vuvlo_on desired turn ? on voltage threshold, r1 and r2 can be calculated using the following equations: r1 r2 r det r2 1.2 v ulvo_on r det
ncp1080 http://onsemi.com 11 when using the external resistor divider, the ncp1080 ha s an external reference voltage hysteresis of 15% typical. inrush and operational current limitations the inrush current limit and the operational current limit are programmed individually by an external rinrush and rilim1 resistors respectively connected between inrush and vportn 1,2 , and between ilim1 and vportn 1,2 as shown in figure 9. ilim1 / inrush vdda1 vbg1 vdda1 vportnx ilim_ref ncp1080 figure 9. current limitation configuration (inrush & ilim1 pins) ilim1 vds_pgood threshold vportnx pass switch inrush i_pass_switch ncp1080 rtn vds_pgood 0 1 vdda1 vdda1 1 v / 9.2 v 2 v current_limit_on & detector figure 10. inrush and ilim1 selection mechanism vdda1 when vport reaches the uvlo_on level, the cpd capacitor is charged with the inrush current (in order to limit the internal power dissipation of the pass ? switch). once the cpd capacitor is fully charged, the current limit switches from the inrush current to the current limit level (ilim1) as shown in figure 10. this transition occurs when both following conditions are satisfied: 1. the vds of the pass ? switch is below the vds_pgood low level (1 v typical). 2. the pass ? switch is no longer in current limit mode, meaning the gate of the pass ? switch is ?high? (above 2 v typical). the operational current limit will stay selected as long as vds_pgood is true (meaning that rtn ? vportn 1,2 is below the high level of vds_pgood). this mechanism allows a current level transition without any current spike in the pass ? switch because the operational current limit (ilim1) is enabled once the pass ? switch is not limiting the current anymore, meaning that the cpd capacitor is fully charged. thermal shutdown the ncp1080 includes thermal protection which shuts down the device in case of high power dissipation. once the thermal shutdown (tsd) threshold is exceeded, following blocks are turned off: ? dc ? dc controller ? pass ? switch ? vddh and vddl regulators ? class regulator when the tsd error disappears and if the input line voltage is still above the uvlo level, the ncp1080 automatically restarts with the current limit set in the inrush state, the dc ? dc controller is disabled and the css
ncp1080 http://onsemi.com 12 (soft ? start capacitor) discharged. the dc ? dc controller becomes operational as soon as rtn ? vportn 1,2 is below the vds_pgood threshold. dc ? dc converter controller the ncp1080 implements a current mode dc ? dc converter controller which is illustrated in figure 11. vddl fb cs 360 mv oscillator comp ss gate driver pwm comp osc vddl vddl blanking time current slope compensation 2 soft ? start r s q 1.45 v 1.2 v current limit comp 0 9 v ldo 3.3 v ldo gate vddh artn vportp set clk reset clk figure 11. dc ? dc controller block diagram 5 k 10 a 11 k 5 a internal vddh and vddl regulators and gate driver an internal linear regulator steps down the vportp voltage to a 9 v output on the vddh pin. vddh supplies the internal gate driver circuit which drives the gate pin and the gate of the external power mosfet. the ncp1080 gate driver supports an external mosfet with high vth and high input gate capacitance. a second ldo regulator steps down the vddh voltage to a 3.3 v output on vddl. vddl powers the analog circuitry of the dc ? dc controller. in order to prevent uncontrolled operations, both regulators include power ? on ? reset (por) detectors which prevent the dc ? dc controller from operating when either vddh or vddl is too low. in addition, an over ? voltage lockout (ovlo) on the vddh supply disables the gate driver in case of an open ? loop converter with a configuration using the bias winding of the transformer (see figure 4). both vddh and vddl regulators turn on as soon as vport reaches the vuvlo_on threshold. error amplifier in non ? isolated converter topologies, the high gain internal error amplifier of the ncp1080 and the internal 1.2 v reference voltage regulate the dc ? dc output voltage. in this configuration, the feedback loop compensation network should be inserted between the fb and comp pins as shown in figures 3, 4 and 5. in isolated topologies the error amplifier is not used because it is already implemented externally with the shunt regulator on the secondary side of the dc ? dc controller (see figure 2). therefore the fb pin must be strapped to artn and the output transistor of the opto ? coupler has to be connected on the comp pin where an internal 5 k pull ? up resistor is tied to the vddl supply (see figure 11). soft ? start the soft ? start function provided by the ncp1080 allows the output voltage to ramp up in a controlled fashion, eliminating output voltage overshoot. this function is programmed by connecting a capacitor c ss between the ss and artn pins. while the dc ? dc controller is in por, the capacitor c ss is fully discharged. after coming out of por, an internal current source of 5 a typically starts charging the capacitor c ss to initiate soft ? start. when the voltage on ss pin has reached 0.45 v (typical), the gate driver is enabled and dc ? dc operation starts with a duty cycle limit which increases with the ss pin voltage. the soft ? start function is finished when the ss pin voltage goes above 1.6 v for which the duty cycle limit reaches its maximum value of 80%. soft ? start can be programmed by using the following equation: t ss (ms) 0.23 c ss (nf)
ncp1080 http://onsemi.com 13 current limit comparator the ncp1080 current limit block behind the cs pin senses the current flowing in the external mosfet for current mode control and cycle ? by ? cycle current limit. this is performed by the current limit comparator which, on the cs pin, senses the voltage across the external rcs resistor located between the source of the mosfet and the artn pin. the ncp1080 also provides a blanking time function on cs pin which ensures that the current limit and pwm comparators are not prematurely trigged by the current spike that occurs when the switching mosfet turns on. slope compensation circuitry to overcome sub ? harmonic oscillations and instability problems that exist with converters running in continuous conduction mode (ccm) and when the duty cycle is close or above 50%, the ncp1080 integrates a current slope compensation circuit. the amplitude of the added slope compensation is typically 110 mv over one cycle. as an example, for an operating switching frequency of 250 khz, the internal slope provided by the ncp1080 is 27.5 mv/ a typically. dc ? dc controller oscillator the frequency is configured with the rosc resistor inserted between osc and artn, and is defined by the following equation: r osc (k ) 38600 f osc (khz) the duty cycle limit is fixed internally at 80%.
ncp1080 http://onsemi.com 14 package dimensions ? 20 ep case 948ab ? 01 issue o dim d min max 6.60 millimeters e1 4.30 4.50 a 1.10 a1 0.05 0.15 l 0.50 0.70 e 0.65 bsc p --- 4.20 c 0.09 0.20 c1 0.09 0.16 b 0.19 0.30 b1 0.19 0.25 l2 0.25 bsc m 0 8 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.07 in excess of the lead width at mmc. dambar cannot be loacted on the lower radius or the foot of the lead. 4. dimensions b, b1, c, c1 to be measured be- tween 0.10 and 0.25 from lead tip. 5. datums a and b are are determined at datum h. datum h is loacted at the mold parting line and coincident with lead where the lead exits the plastic body. 6. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension e1 does not include interlead flash or protrusion. in- terlead flash or protrusion shall not ex- ceed 0.15 per side. d and e1 are determined at datum h. pin 1 reference d e1 0.08 a section b ? b b b1 cc1 seating plane 20x b e e detail a 6.40 --- 4.30 20x 0.98 20x 0.35 0.65 dimensions: millimeters pitch soldering footprint* l l2 gauge detail a e/2 detail b a2 0.85 0.95 e 6.40 bsc p1 --- 3.00 plane seating plane c h b b b m end view a-b m 0.10 d c top view side view a-b 0.20 d c 110 11 20 b a d detail b 2x 10 tips a1 a2 c 0.05 c c p p1 bottom view 3.10 6.76 20x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
ncp1080 http://onsemi.com 15 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp1080/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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